Receive Network Processing Unit (Rx NPU) Figure 9-4 illustrates a simplified receive-side processing pipeline, starting from the moment a Pa...

Virtual Output Queue (VOQ) The Silicon One VOQ Architecture Instead of using dedicated deep interface buffers for packet queuing, Cisco Sili...

Receive Interface Group (Rx IFG) Ingress Pre-Processing and Integrity The Receive Interface Group (Rx IFG) is the ingress pre-processing sta...

 Introduction The previous chapter introduced the Ultra Ethernet (UE) Transport Layer and its endpoint-centric congestion control mechanisms...

 Introduction Receiver Credit-Based Congestion Control (RCCC) is a cornerstone of the Ultra Ethernet transport architecture, specifically de...

Figure 6-14 depicts a demonstrative event where Rank 4 receives seven simultaneous flows (1). As these flows are processed by their respecti...

Inflight Packet Adjustment Figure 6-12 depicts the ACK_CC header structure and fields. When NSCC is enabled in the UET node, the PDS must us...

Network-Signaled Congestion Control (NSCC) The Network-Signaled Congestion Control (NSCC) algorithm operates on the principle that the netwo...

 Ultra Ethernet Transport (UET) uses a vendor-neutral, sender-specific congestion window–based congestion control mechanism together with fl...

Calculating Base RTT [Edit: January 7 2026, RTT role in CWND adjustment process] As described in the previous section, the Bandwidth-Delay P...

Congestion Control Context Updated 5.1.2026: Added CWND computation example into figure. Added CWND cmputaiton into text. Updated 13.1.2026:...

 Introduction Figure 6-1 depicts a simple scale-out backend network for an AI data center. The topology follows a modular design, allowing t...